This specification relates to techniques for providing a translation lookaside buffer configurable to support different memory page sizes.
Translation lookaside buffers (TLBs) are specialized cache structures for optimizing the translation of virtual memory addresses to physical memory addresses in systems using segmented or virtual memory. In such systems, each process addresses its memory space using virtual addresses, which are separate from the physical addresses of the actual memory locations storing the process data. The mapping from virtual addresses to physical addresses is stored in a page table. A TLB stores frequently used virtual address to physical address mappings to avoid having to access the page table for each address translation in order to improve memory performance.